Federal Circuit Affirms PTAB Obviousness Rulings Against Netlist on Two Memory Module Patents

On November 13, 2026, the Federal Circuit decided In re Netlist, Inc., Nos. 2025-1286 and 2025-1296, Netlist's appeals from two decisions of the Patent Trial and Appeal Board in IPR2023-00454, IPR2023-00455, IPR2023-01141, and IPR2023-01142. The Board had determined all claims of U.S. Patent Nos. 11,093,417 and 9,858,215 unpatentable as obvious over U.S. Patent No. 7,363,422 in view of the DDR2 SDRAM Specification (JESD79-2) published by the Joint Electron Device Engineering Council (JEDEC). Both patents are titled "Memory Module with Data Buffering." The parties agreed that there are no material differences between the claims of the two patents for purposes of the appeal, so the court treated the '417 patent as representative (Op. 1-3). Circuit Judge Dyk wrote for a panel that also included Circuit Judges Linn and Chen.

The petitioners were Samsung Electronics Co., Ltd. and Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC. According to the opinion, Samsung Electronics settled with Netlist and filed a notice of nonparticipation before oral argument, the Micron parties settled with Netlist and withdrew after oral argument, and the USPTO declined to intervene. The court wrote that "a live controversy regarding the patentability of Netlist's claims remains before us for resolution" (Op. 3 n.1).

The claims

Claim 1 of the '417 patent recites a memory module with a printed circuit board; logic that receives input address and control signals, including input chip select signals, and outputs registered address and control signals and data buffer control signals; memory devices arranged in ranks that correspond to the registered chip select signals; and circuitry between the data signal lines of the memory bus and the memory devices that transfers data in response to the data buffer control signals and in accordance with an overall CAS latency of the module. The claim requires that data transfers through the circuitry be registered for an amount of time delay such that the module's overall CAS latency is greater than the actual operational CAS latency of each memory device (Op. 3-5).

The petitioners relied on the buffer device of the '422 patent for the claimed circuitry and on JESD79-2 for chip select signals, which the '422 patent did not specifically disclose. On appeal, Netlist did not argue that the combination would fail to satisfy the claim limitations. It argued that a skilled artisan would have lacked a motivation to combine because, according to Netlist, the '422 patent disclosed memory modules only for the Rambus architecture, which was not compatible with the claimed chip select signals, and the combination would be non-functional for Rambus and would "cripple core functionalities described as benefits" in the '422 patent, including backward compatibility with existing generations of memory devices (Op. 6-7).

The prior art's intended purpose

The court wrote that "Netlist misconceives the law of obviousness." Quoting its precedent, it said the motivation-to-combine inquiry "is not whether a relevant artisan would combine a first reference's feature with a second reference's feature to meet requirements of the first reference that are not requirements of the claims at issue," and that "the intended purpose of [the prior art] does not control." Because the claimed invention "is directed to the ability to function in a JEDEC-compliant architecture," the court concluded that the combination's incompatibility with Rambus and its failure to serve the reference's backward-compatibility objectives were "irrelevant" (Op. 8-10).

The court described limited circumstances in which the purpose of a prior-art device is pertinent, for example where the reference itself supplies the asserted motivation to combine, as in In re Gordon, or where the defeated purpose is shared with the challenged claims, as in Polaris Industries, Inc. v. Arctic Cat, Inc. and Medtronic, Inc. v. Teleflex Innovations S.à.r.l. It found neither here: the petitioners did not rely on the '422 patent's Rambus capabilities to establish a motivation to combine, and neither Rambus compatibility nor backward compatibility with Rambus architecture was a shared purpose of the invention (Op. 10-12). The court also rejected Netlist's argument that the Board ignored its backward-compatibility argument in violation of the Administrative Procedure Act (Op. 12 n.6).

Motivation to combine

The court held that substantial evidence supported the Board's findings that the '422 patent disclosed alternative embodiments amenable to JEDEC architectures, including bussed topologies, 64-bit module data widths, and row and column address strobe lines; that the reference's disclosure was concerned with more than one type of memory module; and, with support from Netlist's own expert testimony, that "JEDEC-compliant modules were dominant in the market at the relevant time." The opinion ends with "AFFIRMED" (Op. 13-14).

The companion appeal on the '912 patent

The same panel decided a separate Netlist appeal the same day. In In re Netlist, Inc., No. 2024-2304, a nonprecedential opinion by Circuit Judge Chen, the court affirmed the Board's final written decision in IPR2022-00615 and IPR2023-00203 that claim 16 of U.S. Patent No. 7,619,912 is unpatentable under 35 U.S.C. 103 in view of U.S. Patent Application Publication No. 2006/0277355. The court wrote: "Because the Board did not err in its claim construction, and substantial evidence supports the Board's findings on priority and obviousness, we affirm" (No. 2024-2304, Op. 1-2).